1. Field of the Invention
The present invention relates to a signal delay circuit and a signal delay method, and particularly relates to a signal delay circuit and a signal delay method, which mix delay signals with different delay amount.
2. Description of the Prior Art
FIG. 1 illustrates a prior art signal delay circuit. As shown in FIG. 1, the signal delay circuit 100 includes a plurality of continuous delay stages 101-109. The delay stage 101 delays an input signal IN to generate a delay signal DS1, and the delay stage 103 delays the delay signal DS1 from a previous delay stage to generate a delay signal DS2 . . . . That is, the outputs of each delay stage has different delay amounts from the input signal IN. After that, the signal delay circuit utilizes a multiplexer 111 to select one of the delay signals DS1, DS2 . . . DSn-1, DSn as the output signal OUT. However, complicated design for the multiplexer 111 is needed in this structure. Also, some delay will be caused to the signals. Furthermore, higher accuracy for signals is needed since speed of modern electronic devices largely increases. Therefore, the signal delay circuit 100 needs more delay stages to reach such requirement. Thereby the circuit region increases and the complexity for controlling the signal delay circuit 100 goes up as well.
In some signal delay circuits, a plurality of multiplexers are utilized as delay stages, and a plurality of control signals are applied thereon to select. However, more than two output terminals and more than two multiplexers are needed for this structure. Accordingly, more circuit region is needed and hard to be controlled. Besides, such structure causes more input loading.
Therefore, a signal delay circuit and a signal delay method are needed to improve above-mentioned problems.